proka_kernel/libs/
msr.rs

1//! Model-Specific Registers (MSRs) definitions
2
3/// APIC Location and Status (R/W) See Table 35-2. See Section 10.4.4, Local APIC  Status and Location.
4pub const IA32_APIC_BASE: u32 = 0x1b;
5
6/// If ( CPUID.01H:ECX.[bit 21]  = 1 )
7pub const IA32_X2APIC_EOI: u32 = 0x80b;
8
9/// x2APIC Spurious Interrupt Vector register (R/W)
10pub const IA32_X2APIC_SIVR: u32 = 0x80f;
11
12/// x2APIC ID register (R/O) See x2APIC Specification.
13pub const IA32_X2APIC_APICID: u32 = 0x802;
14
15/// If ( CPUID.01H:ECX.[bit 21]  = 1 )
16pub const IA32_X2APIC_VERSION: u32 = 0x803;
17
18/// x2APIC Task Priority register (R/W)
19pub const IA32_X2APIC_TPR: u32 = 0x808;
20
21/// x2APIC Processor Priority register (R/O)
22pub const IA32_X2APIC_PPR: u32 = 0x80a;
23
24/// x2APIC Logical Destination register (R/O)
25pub const IA32_X2APIC_LDR: u32 = 0x80d;
26
27/// x2APIC In-Service register bits [31:0] (R/O)
28pub const IA32_X2APIC_ISR0: u32 = 0x810;
29
30/// x2APIC In-Service register bits [63:32] (R/O)
31pub const IA32_X2APIC_ISR1: u32 = 0x811;
32
33/// x2APIC In-Service register bits [95:64] (R/O)
34pub const IA32_X2APIC_ISR2: u32 = 0x812;
35
36/// x2APIC In-Service register bits [127:96] (R/O)
37pub const IA32_X2APIC_ISR3: u32 = 0x813;
38
39/// x2APIC In-Service register bits [159:128] (R/O)
40pub const IA32_X2APIC_ISR4: u32 = 0x814;
41
42/// x2APIC In-Service register bits [191:160] (R/O)
43pub const IA32_X2APIC_ISR5: u32 = 0x815;
44
45/// x2APIC In-Service register bits [223:192] (R/O)
46pub const IA32_X2APIC_ISR6: u32 = 0x816;
47
48/// x2APIC In-Service register bits [255:224] (R/O)
49pub const IA32_X2APIC_ISR7: u32 = 0x817;
50
51/// x2APIC Trigger Mode register bits [31:0] (R/O)
52pub const IA32_X2APIC_TMR0: u32 = 0x818;
53
54/// x2APIC Trigger Mode register bits [63:32] (R/O)
55pub const IA32_X2APIC_TMR1: u32 = 0x819;
56
57/// x2APIC Trigger Mode register bits [95:64] (R/O)
58pub const IA32_X2APIC_TMR2: u32 = 0x81a;
59
60/// x2APIC Trigger Mode register bits [127:96] (R/O)
61pub const IA32_X2APIC_TMR3: u32 = 0x81b;
62
63/// x2APIC Trigger Mode register bits [159:128] (R/O)
64pub const IA32_X2APIC_TMR4: u32 = 0x81c;
65
66/// x2APIC Trigger Mode register bits [191:160] (R/O)
67pub const IA32_X2APIC_TMR5: u32 = 0x81d;
68
69/// x2APIC Trigger Mode register bits [223:192] (R/O)
70pub const IA32_X2APIC_TMR6: u32 = 0x81e;
71
72/// x2APIC Trigger Mode register bits [255:224] (R/O)
73pub const IA32_X2APIC_TMR7: u32 = 0x81f;
74
75/// x2APIC Interrupt Request register bits [31:0] (R/O)
76pub const IA32_X2APIC_IRR0: u32 = 0x820;
77
78/// x2APIC Interrupt Request register bits [63:32] (R/O)
79pub const IA32_X2APIC_IRR1: u32 = 0x821;
80
81/// x2APIC Interrupt Request register bits [95:64] (R/O)
82pub const IA32_X2APIC_IRR2: u32 = 0x822;
83
84/// x2APIC Interrupt Request register bits [127:96] (R/O)
85pub const IA32_X2APIC_IRR3: u32 = 0x823;
86
87/// x2APIC Interrupt Request register bits [159:128] (R/O)
88pub const IA32_X2APIC_IRR4: u32 = 0x824;
89
90/// x2APIC Interrupt Request register bits [191:160] (R/O)
91pub const IA32_X2APIC_IRR5: u32 = 0x825;
92
93/// x2APIC Interrupt Request register bits [223:192] (R/O)
94pub const IA32_X2APIC_IRR6: u32 = 0x826;
95
96/// x2APIC Interrupt Request register bits [255:224] (R/O)
97pub const IA32_X2APIC_IRR7: u32 = 0x827;
98
99/// If ( CPUID.01H:ECX.[bit 21]  = 1 )
100pub const IA32_X2APIC_ESR: u32 = 0x828;
101
102/// x2APIC LVT Corrected Machine Check Interrupt register (R/W)
103pub const IA32_X2APIC_LVT_CMCI: u32 = 0x82f;
104
105/// x2APIC Interrupt Command register (R/W)
106pub const IA32_X2APIC_ICR: u32 = 0x830;
107
108/// x2APIC LVT Timer Interrupt register (R/W)
109pub const IA32_X2APIC_LVT_TIMER: u32 = 0x832;
110
111/// x2APIC LVT Thermal Sensor Interrupt register (R/W)
112pub const IA32_X2APIC_LVT_THERMAL: u32 = 0x833;
113
114/// x2APIC LVT Performance Monitor register (R/W)
115pub const IA32_X2APIC_LVT_PMI: u32 = 0x834;
116
117/// If ( CPUID.01H:ECX.[bit 21]  = 1 )
118pub const IA32_X2APIC_LVT_LINT0: u32 = 0x835;
119
120/// If ( CPUID.01H:ECX.[bit 21]  = 1 )
121pub const IA32_X2APIC_LVT_LINT1: u32 = 0x836;
122
123/// If ( CPUID.01H:ECX.[bit 21]  = 1 )
124pub const IA32_X2APIC_LVT_ERROR: u32 = 0x837;
125
126/// x2APIC Initial Count register (R/W)
127pub const IA32_X2APIC_INIT_COUNT: u32 = 0x838;
128
129/// x2APIC Current Count register (R/O)
130pub const IA32_X2APIC_CUR_COUNT: u32 = 0x839;
131
132/// x2APIC Divide Configuration register (R/W)
133pub const IA32_X2APIC_DIV_CONF: u32 = 0x83e;
134
135/// If ( CPUID.01H:ECX.[bit 21]  = 1 )
136pub const IA32_X2APIC_SELF_IPI: u32 = 0x83f;
proka_kernel/libs/msr.rs

proka_kernel/libs/
msr.rs
