Expand description
Model-Specific Registers (MSRs) definitions
Constantsยง
- IA32_
APIC_ BASE - APIC Location and Status (R/W) See Table 35-2. See Section 10.4.4, Local APIC Status and Location.
- IA32_
X2APIC_ APICID - x2APIC ID register (R/O) See x2APIC Specification.
- IA32_
X2APIC_ CUR_ COUNT - x2APIC Current Count register (R/O)
- IA32_
X2APIC_ DIV_ CONF - x2APIC Divide Configuration register (R/W)
- IA32_
X2APIC_ EOI - If ( CPUID.01H:ECX.[bit 21] = 1 )
- IA32_
X2APIC_ ESR - If ( CPUID.01H:ECX.[bit 21] = 1 )
- IA32_
X2APIC_ ICR - x2APIC Interrupt Command register (R/W)
- IA32_
X2APIC_ INIT_ COUNT - x2APIC Initial Count register (R/W)
- IA32_
X2APIC_ IRR0 - x2APIC Interrupt Request register bits [31:0] (R/O)
- IA32_
X2APIC_ IRR1 - x2APIC Interrupt Request register bits [63:32] (R/O)
- IA32_
X2APIC_ IRR2 - x2APIC Interrupt Request register bits [95:64] (R/O)
- IA32_
X2APIC_ IRR3 - x2APIC Interrupt Request register bits [127:96] (R/O)
- IA32_
X2APIC_ IRR4 - x2APIC Interrupt Request register bits [159:128] (R/O)
- IA32_
X2APIC_ IRR5 - x2APIC Interrupt Request register bits [191:160] (R/O)
- IA32_
X2APIC_ IRR6 - x2APIC Interrupt Request register bits [223:192] (R/O)
- IA32_
X2APIC_ IRR7 - x2APIC Interrupt Request register bits [255:224] (R/O)
- IA32_
X2APIC_ ISR0 - x2APIC In-Service register bits [31:0] (R/O)
- IA32_
X2APIC_ ISR1 - x2APIC In-Service register bits [63:32] (R/O)
- IA32_
X2APIC_ ISR2 - x2APIC In-Service register bits [95:64] (R/O)
- IA32_
X2APIC_ ISR3 - x2APIC In-Service register bits [127:96] (R/O)
- IA32_
X2APIC_ ISR4 - x2APIC In-Service register bits [159:128] (R/O)
- IA32_
X2APIC_ ISR5 - x2APIC In-Service register bits [191:160] (R/O)
- IA32_
X2APIC_ ISR6 - x2APIC In-Service register bits [223:192] (R/O)
- IA32_
X2APIC_ ISR7 - x2APIC In-Service register bits [255:224] (R/O)
- IA32_
X2APIC_ LDR - x2APIC Logical Destination register (R/O)
- IA32_
X2APIC_ LVT_ CMCI - x2APIC LVT Corrected Machine Check Interrupt register (R/W)
- IA32_
X2APIC_ LVT_ ERROR - If ( CPUID.01H:ECX.[bit 21] = 1 )
- IA32_
X2APIC_ LVT_ LINT0 - If ( CPUID.01H:ECX.[bit 21] = 1 )
- IA32_
X2APIC_ LVT_ LINT1 - If ( CPUID.01H:ECX.[bit 21] = 1 )
- IA32_
X2APIC_ LVT_ PMI - x2APIC LVT Performance Monitor register (R/W)
- IA32_
X2APIC_ LVT_ THERMAL - x2APIC LVT Thermal Sensor Interrupt register (R/W)
- IA32_
X2APIC_ LVT_ TIMER - x2APIC LVT Timer Interrupt register (R/W)
- IA32_
X2APIC_ PPR - x2APIC Processor Priority register (R/O)
- IA32_
X2APIC_ SELF_ IPI - If ( CPUID.01H:ECX.[bit 21] = 1 )
- IA32_
X2APIC_ SIVR - x2APIC Spurious Interrupt Vector register (R/W)
- IA32_
X2APIC_ TMR0 - x2APIC Trigger Mode register bits [31:0] (R/O)
- IA32_
X2APIC_ TMR1 - x2APIC Trigger Mode register bits [63:32] (R/O)
- IA32_
X2APIC_ TMR2 - x2APIC Trigger Mode register bits [95:64] (R/O)
- IA32_
X2APIC_ TMR3 - x2APIC Trigger Mode register bits [127:96] (R/O)
- IA32_
X2APIC_ TMR4 - x2APIC Trigger Mode register bits [159:128] (R/O)
- IA32_
X2APIC_ TMR5 - x2APIC Trigger Mode register bits [191:160] (R/O)
- IA32_
X2APIC_ TMR6 - x2APIC Trigger Mode register bits [223:192] (R/O)
- IA32_
X2APIC_ TMR7 - x2APIC Trigger Mode register bits [255:224] (R/O)
- IA32_
X2APIC_ TPR - x2APIC Task Priority register (R/W)
- IA32_
X2APIC_ VERSION - If ( CPUID.01H:ECX.[bit 21] = 1 )